A frequency synthesizer generates a signal at a selected frequency that is within an operational frequency range of the frequency synthesizer, and the selected frequency is derived from the output of a time base or oscillator that typically has a fixed or constant frequency. Frequency synthesizers are found in many modern devices including, but not limited to, radio transceiver apparatuses, mobile telephones, radiotelephones, two-way radio systems, CB radios, satellite receivers, GPS systems, etc. Synthesizers commonly utilize a phase-locked loop (PLL) to produce a desired frequency output from a controlled oscillator at the desired frequency. The frequency of the controlled oscillator is typically controlled by a voltage at a control input, and hence such a controlled oscillator is known as a voltage controlled oscillator (VCO). The output frequency of a PLL synthesizer in the locked condition is determined by the loop divide number. In fractional-N (or so-called FRAC-N) frequency synthesizers the loop divide number can have a fractional portion in addition to an integer portion. FRAC-N frequency synthesizers are particularly valued because of their ability to achieve fine frequency resolution and effectively manage the compromise between lock time and sideband noise. Some FRAC-N synthesizers dynamically switch between different integer loop divide values, one at a time, to produce a sequence of divide values so that on the average an integer plus a fractional divide number is effectively obtained over a period of time. The number of different integer loop divide values available for selection by this dynamic switching action is typically 2K, where K is a number of digital accumulators within the synthesizer. For example, a synthesizer having two accumulators utilizes a set of four different integer loop divide numbers; a synthesizer having three accumulators utilizes a set of eight different loop divide numbers; etc. The set of integer divide numbers are typically adjacent integer values, but this is not essential.
One of the concerns in designing a FRAC-N synthesizer is the single sideband noise (SBN) created about the desired output signal. There are several sources of noise that contribute to the output SBN, including noise produced by the phase (or phase frequency) detector and charge pump, SBN produced by the fixed frequency reference, SBN produced by the VCO, noise produced by the divider and noise produced by the FRAC-N process in switching between divide numbers. The noise contributions at the output of the frequency synthesizer from many of these sources are increased by 20 Log(Fout/Fref), where Fout is the frequency of the synthesizer and Fref is the frequency of the fixed frequency reference. The frequency synthesizer's loop filter can be designed such that most of the noise sources contributing to the output SBN are reduced at offset frequencies beyond the loop bandwidth of the frequency synthesizer. This is an effective strategy but it constrains the loop bandwidth to less than desirable values when output SBN is an important design consideration. As a result, the loop divide number (Fout/Fref) becomes a limiting factor. Thus, phase noise considerations dictate using a fixed reference frequency that has a frequency as large as possible while still allowing synthesis of the desired synthesized frequency. Of course, that is countered by considerations such as channel spacing and cost, among others.
In selecting a fixed frequency reference source for a frequency synthesizer, cost, short term stability and long term stability are important factors. Short term stability relates to the SBN and long term stability refers to the change in frequency over temperature, voltage, process, and time. Fixed frequency reference sources, such as crystal oscillators can have excellent short term stability and the long term stability can be improved using compensation, and are referred to as temperature compensated crystal oscillators (TCXO). Some of the more popular TCXOs operate in the range of 15-40 MHz. However, using frequency references in this range for synthesizing frequencies in the 800 MHz to 1 GHz range requires a loop divide number sufficiently high so as to necessitate a low pass loop filter design yielding a closed loop bandwidth on the order of 1.5 KHz to meet desired SBN levels for two-way radio applications. For typical voice channels having a bandwidth on the order of 3 KHz, a closed loop bandwidth of 1.5 KHz prevents sufficient frequency modulation when the modulation is applied to the loop at a single port. In lower bands, such as the VHF band (30 MHz to 300 MHz), creating a frequency modulated (FM) carrier is difficult to accomplish even with a reference frequency at 15 MHz. The loop divide numbers associated with this band would range from 2 to 20 with a 15 MHz reference. It has been established that 20 is the lowest average loop divide number needed to have the phase frequency detector operate in the linear region compatible with a 3rd order FRAC-N synthesizer. Current solutions would be to use a frequency divider after the fixed frequency reference source before the signal is applied to the phase detector or use a frequency divider on the output signal of the PLL to obtain a lower frequency at the output of the divider.
The limiting aspects of using a TCXO in the range of 15-40 MHz requiring a closed loop bandwidth on the order of 1.5 KHz to 4 KHz has resulted in the use of a two port frequency modulation scheme that has been in use for years for constant envelope applications like frequency modulation, phase modulation, and complex modulation such as quadrature phase shift keying modulation. In a conventional two port modulator the low frequency modulation is performed digitally, using FRAC-N techniques, while the higher frequency component of the modulation signal is applied to the VCO via an analog path where some of the digital information is used to generate an analog signal that is added to the control input of the VCO. Thus, as information to be transmitted comes into the modulator, it is processed and split between the digital low frequency port and the analog high frequency port. The two port modulation approach requires careful tuning of amplitude and delay in each port path to ensure that the high frequency and low frequency modulation components are applied to the VCO control input to achieve the desired response over the modulation bandwidth.
Two port modulators, by nature of their design, are very sensitive to component value variations. Because of variations in component values, each modulator must be characterized upon manufacture to adjust signal levels, timing and other aspects of the modulator. Performing the characterization is time consuming and generally considered a gating operation in manufacturing. If the loop noise could be substantially reduced, then the closed loop bandwidth could be widened sufficiently to use just the digital low frequency port, all digital modulation, which would be a substantial advantage over two port modulators.
Accordingly, there is a need for a method and apparatus for low noise single port frequency modulation using a FRAC-N modulator.
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The apparatus and method components have been represented where appropriate by conventional symbols in the drawings, showing only those specific details that are pertinent to understanding the embodiments of the present invention so as not to obscure the disclosure with details that will be readily apparent to those of ordinary skill in the art having the benefit of the description herein.